Computer having floating point division



Feb. 22, 1966 Filed Oct. 1, 1962 A REGISTER Frac tion as 1 1s [41I40I39I3s 37 36 35|a4 [33 32 a1|30 29|2s[27[26|25|24l23|22|21|20119|18|17|16|15|14|13|12|11|10 9 8 I 7] 6 5 4 3| 2 I 1] "ON 19 H NUMBER (FRACTION) x 2 T. M. HERTZ COMPUTER HAVING FLOATING POINT DIVISION NUMBER 14 Sheets-Sheet 1 FIG.

INVENTOR." THEODORE M. HERTZ ATTORNEY- 1'. M. HERTZ 3,236,999

COMPUTER HAVING FLOATING POINT DIVISION 14 Sheets-Sheet 2 an @3335 was": 0: m 30 m6 n o m5 v v Fm INVENTOR. THEODORE M. msmz BY ZV a a! ATTORNEY 7 0:25.58 use -vhououonp om no mug. #avaomxo v QQOQQHHHHHHHHQQ SS TI. flu pm. ao pum m auwqomx 7.

111m -L m m STlmlmlfiFHTLSFHFlowETNKNT TNTNTN mm mm 02% @2271" 5mm Fm mm mm 3 S Filed Oct. 1, 1962 Feb. 22, 1966 Feb. 22, 1966 T. M. HERTZ COMPUTER HAVING FLOATING POINT DIVISION 14 Sheets-Sheet 5 Filed Oct. 1, 1962 TIMING AND FLIP FLOPS INPUT INPUT COD E SELECTION I OPERATION TO CONTROL READ AND WRITE MEMORY MATRICES GFFI O REGISTER C REGISTER INDICATOR AND CONTROL ypgwm OUTPUT SELECTOR INVENTOR. THEODORE M. HERTZ FIG.

FROM

FROM K9 T0 ll INPUT ATTORNEY Feb. 22, 1966 T. M. HERTZ 3,236,999

COMPUTER HAVING FLOATING POINT DIVISION INVENTOR. THEODORE M. HERTZ ATTORNEY Feb. 22, 1966 T. M. HERTZ 3,236,999

COMPUTER HAVING FLOATING POINT DIVISION Filed 11 1962 14 Sheets-Sheet 00 IO}! Input number of characters from device specified 01 OCH Output number of characters from device specified 02 ALS Shift number in A register left by amount specified 02 .2 ASV Same as 02 with overflow indication of 1 lost 02 .4 ASC Same as 02 with normalizing optional termination 03 ARS Shift A register right by amount specified O5 STR Store number in R register in address specified TIX Transfer to new location count if index 0, decrement l1 TNZ Transfer if number in A register is not equal to zero 12 SAP Set sign of A register positive 12 .4 SAN Set sign of A register negative 13 CSA Change sign of the A register 15 TLB Transfer if the least significant bit of A is a one 16 CAZ Clear A register to plus zero 16.4 CMZ Clear A register to minus zero 17 CMP One's complement A register bits, including sign 17.4 RND Round A register number if most significant R bit is 1 25.1 STI Store index in right hand address portion specified 31.1 LDI Read index from right hand portion of address to G41 CMG Compare, set Jo true for B A, false for B A 35.4 (IVIE Compare, set Jo true for B A or B A, false for B A 36 CLS Clear A register and subtract addressed operand 37 CLA Clear A register and add addressed operand thereto 40 CTL Copy from address specified to L loop to end of loop 41 CTV Copy from address specified to V loop to end of loop 42 LLS Long left shift A and R registers by amount specified 42.2 LSV Same as 42 with overflow for loss of a 1 by shift 42.4 LSC Same as 42 with normalizing optional termination 43 LBS Long right shift of A and R registers 44 CFL Copy from L loop to Main memory starting at address 45 STO Store number in A register in address specified TZE Transfer if number in A register is zero 51 TBA Transfer unconditionally 52 TOV Transfer on overflow (no halt if overflow) 53 TMI Transfer if A register sign is negative 54 NOP N0 operation 55 TPL Transfer if A register sign is positive 56 XAR Interchange A and R registers 57 CAR Copy A register into the R register, clear A 63 MPY Multiply A number by operand in address specified 65 STA Store address in A register in address specified 66 DIV Divide A number by operand in address specified 70 EXT Logical multiplication of A number by operand specified 71 HTR Halt and transfer unconditionally 72 SUB Subtract operand specified from A register number 73 ADD Add operand specified to A register number 76 RCS Clear and subtract (Copy A to R) 77 RCA Clear and Add (Copy A to R) 23 MP Floating Multiply 26 FDV Floating Divide 74 F513 Floating Subtract 75 FAD Floating Add Assume overflow was off; if overflow was on initially then if B A 0, do

nothing; if B A 0, reverse Jo FIG. 5 INVENTOR. THEODORE M. HERTZ iii-CW4 ATTORNEY Feb. 22, 1966 T. M. HERTZ 3,236,999

COMPUTER HAVING FLOATING POINT DIVISION Filed Oct. 1, 1962 14 Sheets-Sheet 6 InDo Phase (IWT) FLOATING DIVIDE MODE 1. Computer is set for floating divide (code 26) 2. Divisor is copied into B register (Dividend is assumed to be in A register originally) 3. 32 count set up in G register 4-. Test to see if B A, if so:

180 Ahl'BhlIIRh-Q' Oec T2 Fm (Reset initially) if B A Dec Ahl Bhl' I1 Rh2' 5. Exponent is excluded from number comparison 6. Prepare for divide operation in U1 phase 7. If B A (normal divide case) force operation code 66 for fixed point divide INVENTOR. THEODORE M. HERTZ BYj M ATTORNEY Feb. 22, 1966 T. M. HERTZ COMPUTER HAVING FLOATING POINT DIVISION 14 Sheets-Sheet 7 Filed 0ct.- 1, 1962 .8 m3 NH E 332 8 .8 m? .8 NH 5 II II 33 E Fido mm mPZwm .ma 8 m n wuo umhdouo Q AmC aonhonnm o $2 @002 MEHBHH ozHnawQHm INVENTOR. THEODORE M. HERTZ BY f 4 C 5 ATTORNEY ,7

Feb. 22, 1966 T. M. HERTZ 3,236,999

COMPUTER HAVING FLOATING POINT DIVISION Filed Oct. 1, 1962 14' Sheets-Sheet a U1 Phase (1w) (Continued) FIDATING DIVIDE MODE 9. Zero dividend 10. Copy difference between exponents into B register (change operation code from 66 to 72) 11. (Convert back to 66 at end. of D1) 011 Fm T l-1 16.3 Fm Th1 I2 16.1 Fm I2 Th1 FIG. 70

INVENTOR. THEODORE M. HERTZ ezogew ATTORNEY Feb. 22, 1966 T. M. HERTZ 3,236,999

COMPUTER HAVING FLOATING POINT DIVISION Filed Oct. 1, 1962 14 Sheets-Sheet 9 U1 Phase (31%) FLOATING DIVIDE FDDE 1. Fixed point division logic used. for each word 2. Gate into subtrector (from Tl-T32) Orl lrl FmIZ'ili EDo'Tl II II 3. Copy quotient bits into R 42 according to state of D1 11 42 01 42 16.1 Odl Mg D6 D1' 12' T1 (Quotient bit one) M2 D1 12' T1 (Quotient bit zero) H KB. w Fm I2 m' Al Ka. 13; Fm D3 D0 II II II H h. After 32 word times set Do for entering Ui Do phase (last word time of divide) Ui D0 Phase (lWT) FLOATING DIVIDE MDDE 1. Copy quotient bite into A register lab-l M2 E Do 1 41' can], R142 E Do Thl' 2. Convert to clear and add at 132 time 3. Copy exponent from B register to A register lahl 131 02 D2 Oahl 131' 34 o o De Copy stored. sign of quotient into A register lab]. C2 I38. K 41 Ca l-l 02' Ilia E 5 Terminate operation INVENTOR. FIG.9 THEODORE M. HERTZ JD- M ATTORNEY Feb, 22, 1966 T. M. HERTZ COMPUTER HAVING FLOATING POINT DIVISION 14 Sheets-Sheet 10 Filed Oct. 1, 1962 INVENTOR. THEODORE M. HERTZ BYjil' M4.

O- GE ATTOR NEY T. M. HERTZ COMPUTER HAVING FLOATING POINT DIVISION l Emzomxm 8 mm NF 29.5259 N o 20:53 .NE L E 5 J vm F o Feb. 22, 1966 Filed Oct. 1, 1962 .8 9.5.8 IL: at 264 2 INVENTOR. THEODORE M. HERTZ jo L ATTORNEY Feb. 22, 1966 T. M. HERTZ COMPUTER HAVING FLOATING POINT DIVISION 14 Sheets-Sheet 12 Filed 00tl, 1962 LL MO mu ovm .vo

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ATTORNEY Feb. 22, 1966 T. M. HERTZ COMPUTER HAVING FLOATING POINT DIVISION Filed Oct. .1, 1962 14 Sheets-Sheet 15 TiEODORE M. HERTZ ATTORNEY Feb. 22, 1966 T. M. HERTZ 3,236,999

COMPUTER HAVING FLOATING POINT DIVISION Filed Oct. 1, 1962 l4 Sheets-Sheet 14 .IL L

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J 3:: SE 1 I INVENTOR. THEODORE M. HERTZ BY J (1. W '5 o m 0 ATTOR NEY United States Patent 3,236,999 COMPUTER HAVING FLOATING POINT DIVISION Theodore M. Hertz, Whittier, Califi, assignor to North American Aviation, Inc. Filed Oct. 1, 1962, Ser. No. 227,366 16 Claims. (Cl. 235-464) This invention relates to electronic digital computers and more particularly to a computer having floating point division capabilities.

Prior art digital computers utilized fixed point arithmetic processes in executing computer operations. In performing fixed point arithmetic processes a computer assumes the binary point (analogous to a decimal point) to be between the sign of a number and the most significant digit of the number. Thus the number is considered to have an absolute value of less than one. As explained in patent application filed approximately September 24, 1962 for Computer Having Floating Point Addition and Floating Point Subtraction invented by me, in order to execute fixed point addition and subtraction operations, numbers to be operated upon by a computer must first be appropriately scaled prior to computation in order to obtain meaningful results. The scaling of the numbers is accomplished prior to entering them into the computer or by shifting them through pro gramming afterwards. Fixed point division numbers need to be scaled prior to performing computation with them. In division hand scaling or shifting of the numbers through programming to a lesser magnitude may be necessary to insure against obtaining a quotient equal to or greater than one which causes or would cause overflow. In division shifting of the result through use of a program is desirable in order to prevent loss of significant portions which should be retained for use in later computations. This is particularly true where after a division operation has been performed, the product or quotient must be added or subtracted from or with other numbers, in which case scaling would first have to be done before the additional computation could be made.

In order to overcome the limitations above, a system has been devised whereby numbers are automatically scaled inside the computer. This system is called herein a floating point arithmetic process. In the floating point format, a word is divided into a sign bit, a characteristic, and a mantissa. The characteristic is the exponent to which the base number 2 is raised. The mantissa is expressed as a binary fraction, as a number less than one. In order to determine the numerical value indicated by the characteristic and mantissa, the base number 2 must first be raised to the value of the characteristic, the results of that operation then multiplied by the fraction represented by the mantissa.

In floating point division, the dividend is initially transferred to a first register and the divisor is transferred to a second register. A counter or third register is set up to terminate the division operation after it has been completed.

As may be deduced from analogizing to logarithms, to divide one number by another merely requires subtracting the exponent portion of the divisor numerical value from the exponent portion of the dividend numerical value. Then the fraction portion of the divisor numerical value is divided into the fraction portion of the dividend numerical value. This latter step, it may be appreciated, is the usual fixed point operation mentioned above.

, A comparison flip-flop .is utilized to determine the comparative value of the fractional portions of the two operands. If the fraction portion of the divisor is larger than the fraction portion of the dividend, the computer 3,2363% Patented Feb. 22, 1966 carries out the fixed point divide operation. However, if the dividend is larger than or equal to the divisor, the' dividend fraction is de-normalized by one bit to make the divisor the larger number.

The term normalization is the opposite of de-nor-malization. The fractional portion is normalized by shifting it left and in order that the numerical value remains unchanged, the exponent is decremented by one for each bit the fractional portion is shifted left. The term denormalization refers to shifting numbers in a particular register to the right a predetermined number of bit positions, usually to align the operand in one register with an operand in another register or to avoid division overflow. The exponent portion of the numerical value involved is incremented by one for each bit of right shifting of the fraction portion. In either case, normalization or de-normalization, it can thus be seen that the value of the number remains the same.

In order to carry out the process of division, an initial subtraction operation is performed using the fractional portions and the difference is transferred to the first register and precessed left one digit. The two exponents are also subtracted and the difference is transferred to the second register. v

When dividing a number with a larger exponent in the first register by a number with a small exponent in the second register, an exponent overflow may occur. If the reverse is true, division of a small exponent number by a large exponent number, an exponent underflow condition may occur. Another flip flop is utilized to detect these conditions, but termination of the operation does not occur in either case. If the dividend or divisor is a zero, however, the division operation is terminated.

The computer then carries out fixed point divide sequence. The quotient bit obtained at each word time is placed in the fourth register which holds each bit of the quotient until all quotient bits have been transferred back to the first register. The exponent of the quotient is also transferred to the first register.

It is therefore an object of this invention to provide a computer having a simplified floating point division.

It is still another object of this invention to provide an improved floating point division operation in a' computer.

Still another object of this invention is to provide serial floating point division in an electronic computer.

A still further object of this invention is to provide floating point division requiring no programmed normalization or de-normalization.

A further object of this invention is to provide an automatic normalizing and de-normalizing floating point operation within a computer.

Another object of this invention is to provide a computer for handling floating point numbers in a more compact form.

A final object of this invention is to provide an entirely automatic floating point division operation within a computer.

Still other objects and features of this invention will become apparent from the following drawings, in which:

FIG. 1 is an illustration of a positive operand having an exponent portion and a fraction portion contained in an accumulator or A register within a computer;

FIG. 2 is an illustration of a negative operand having an exponent portion and a fraction portion contained in an accumulator or A register within a computer;

FIG. 3 is an illustration representing an entire electronic digital computer;

FIG. 4 is an illustration of an accumulator or A register;

FIG. 5 is an explanation of each of the operation codes;

FIG. 6 illustrates logic for InDo phase of the floating divide operation;

FIG. 7 illustrates logic for U1 phase of the floating divide operation;

FIG. 7a illustrates a continuation of the logic for the U1 phase of the floating divide operation;

FIG. 8 illustrates logic for the Ui phase of the floating divide operation;

FIG. 9 illustrates logic for the U'z'Do phase of the floating divide operation;

FIG. 10 illustrates a block diagram of each step of the floating divide operation;

FIG. 11 illustrates an example of logic mechanization for floating divide operation;

FIG. 12 illustrates an example of logic mechanization for floating divide operation;

FIG. 13 illustrates an actual electronic mechanization of the B register recirculation set forth in FIG. 12; and

FIG. 14 is an illustration of a clock gated flip flop suitable for use in the device of the invention.

Referring now to FIG. 1, it is seen that floating point information may be handled in a computer in Words each consisting of 41 bits, the bits being numbered from right to left in order of increasing significance. The first bit is a synchronizing bit and is not utilized in computer operations. Bits 2 through 32 are utilized to indicate in binary form the fraction portion of the particular floating point number being processed. The bits 33 through 40 are used to indicate the exponents, that is, the power to which the number 2 is raised. With such 8 bits, therefore, the number 2 may have any power from zero to 255, however, by introducing a bias of -128, the range is shifted by 128 to a range of l28 through 127 with bit 40 being utilized to indicate Whether the exponent is plus or minus. For example, to represent a number having a negative exponent such as is the case of 2"" bit 40 is false (or zero) and bits 33 through 39 are 0000000. For 2- bits 40 through 33 are 01111111. For 2", bits 40 through 33 are 10000000. For 2 bits 40' through 33 are 10000001. For 2 bits 40* through 33 are 10000010. For2+ as illustrated by FIG. 1, bits 40 through 33 are 10000011. For 2+ bits 40 through 33 are 11111110. For 2+ bits 40 through 33 are 11111111.

Another way to describe the biasing effect is to consider a register having a capability of counting from zero through 255. However, in order to establish a capability of counting below zero, there is included in the computer logic gates to indicate a 01111111 for the exponent (-1, which stands for 2 and there are additional logic gates to cause the computer to count down (1 through 128) from 01111111 to 00000000. If bit 40 is minus then each bit changed to from 1 represents a greater numerical value (disregarding the sign). Thus, 1 represented by 011111 11 would be decremented to 128 represented by 00000000. If bit 40 is plus each decremented bit represents a decrease over a range of 127 through zero. Where the zero is relocated at the center of a registers counting range (the computer formerly being capable of counting from zero to 255, i.e., an 8 bit counter), allotting zero to one of the counts leaves a capability of counting up to +127 and down to 128.

In effect by dividing zero through 255 into two parts by appropriate logic gates, the register counts up from zero through 127 and down from 1 through -128. If bit 40 is minus, the register counts over the negative range. If bit 40 is positive, the register counts over the positive range.

It should be noted that the binary point is assumed to be at the left of the fraction part of the number in FIG. 1. It may also be seen that the exponent is determined by bits 33 through 40, and the fraction is determined by bits 2 through 32. The floating point numher is determined by raising 2 to the exponent indicated and multiplying by the fraction, as shown in FIG. '1.

A negative number is illustrated in FIG. 2. The exponent is expressed in 2s complement form which is obtained by subtracting the negative number from all zeros. The A40 bit is reversed during the multiplication operation so that the product will have the correct sign.

In all floating point operations, logic control is utilized to insure that all operations specified by the instructions are performed in the correct mode and in the proper sequence. Basic control elements in the computer are logic gates and flip flops operating in conjunction with control registers and other registers. The states of the flip flops define the logic control functions of mode designations, operation selection, loop and main memory selection, channel selection, and sector selection.

Flip flops I1, 12, and I4 shown in FIG. 3 are the primary elements controlling the computer through the various modes and in the transitions from one mode to another. Two other flip flops designated as mode selection flip flop Kc and memory write/read gating flip flop D0 are also utilized as control elements. However, both Kc and D0 also perform other functions on a time sharing basis as do a number of other logic flip flops.

A D register comprised of flip flops D1 through D6, illustrated in FIG. 3, defines the type of operation to be performed by the computer. The flip flop settings are determined by the bit configuration and the operation code of each command. Outputs of the flip flops then control the operation control gating matrix to define the type of operation specified.

The C register is comprised of flip flops C1 through C6. The C register holds the channel address code which controls the gating of the write and read switching networks in the selection of a designated memory channel. Outputs of these flip flops enable the write or read head of a selected channel after a desired sector has been located during the sector selection phase.

Sector selection is the procedure which determines the sector location of a designated command or operand in the memory. The Z register, the origin sector channel, and several associated flip flops comprise the sector selection elements.

The control registers (Z and G) and their associated logic circuits perform many of the control functions required in the location storage modification and execution of commands and in the handling of data. The A register is comprised of a Write and read amplifier and 39 bits circulating in the loop register channel. The Z register stores the command pair being executed. The G register, also comprised of a read and write amplifier and 39 bits circulating in the loop register channel, and contains storage space for the location counter, index register. The G register is also used as a computation cycle counter.

The arithmetic registers (A, B, and R) and their associated logic circuits perform the basic computer arithmetic functions of addition, subtraction, multiplication, and division. These registers also perform many semiarithmetic and control functions. In the execution of arithmetic commands the registers utilize two additional flip flops which, during the computations, form an addersubtractor circuit.

The A or accumulator register shown in FIG. 4 stores the information in six flip flops and in 35 bit positions in the loop-register channel. Utilized in all arithmetic computations, the A register accumulates all or a portion of the result of each computation.

The B register shown in FIG. 3 which is also referred to as the number register, utilizes three flip flops and 38 bit positions in the loop register channel. This is an intermediate storage register which is not directly addressable by the programmer. In most instances, the computer first stores a command or operand being read from or written into memory in the B register, and then trans 5 fers the word to the intended locations as required. The remainder or R register shown also in FIG. stores its contents in four flip flops and 37 bit positions in the loop register channel. (R42 and R43 flip flops are not an integral part of the register.) This register may be utilized as an extension of the A register in the execution of multiplication and division commands.

Principal computer elements involved 1n the execution of the arithmetic processes are the three arithmetic registers and the adder-subtractor circuit. The adder-subtractor circuit is comprised of a sum-diiferenceflip flop and a computation carry-borrow flip flop Kn which operates in conjunction with the arithmetic registers to carry out the computations. The flip flops S and Ka are illustrated in FIG. 3. Other computer elements such as the memory read/write circuitry and the control registers also are utilized. However, these other elements perform associated functions which generally enter into virtually lof the com uter o erations. al The three rithmei ic registers and the adder-subtractor circuit are the principal computation elements for both the fixed point and floating point arithmetic processes. However, additional flip flops and primary and secondary gates are necessary to control the floating point processes. For example the computer utilizes the additional flip flop Fa during floating point addition and subtract-ion functions and Fm during floating point multiplication and division functions. Flip flop E is designated as the comparison flip flop for floating point addition, subtraction and multiplication. Primary gates Mg, 1%, M 2, 1L1, and Ui are also utilized during the floating point operat on. i l 0 is used during addition and subtraction operation. 1TH is used during multiplication operation. pg 18 used d ui'ing divide operation. El signifies the second Word time of all word times, and H15 signifies all succeeding word times.

Further explanation of a computer and its operation may be obtained by reference to patent application Serial No. 187,319, filed April 13, 1962 for Computer invented by me. The various operations and modes of a general purpose scientific computer are set forth in that appl cation as well as a description of conventional logic notation. FIG. 5 is a further explanation of each of the codes. It is noted that code 23 (FDV, floating divide) is primarily involved in this description. However, in carrying out this code, other codes are forced (entered). For example, fixed point division, code 66, may be temporarily entered to make use of its right subtraction and right shifting capability. Also, the addition mode 73 may be temporarily entered.

Other modes are entered into as necessary, however, the additional modes entered into are set forth below.

FIGS. 11 and 12 illustrate examples of logic mechanization inside a computer used to perform floating divide operation. Symbols used for and gates and or gates as well as for flip flops are Well known in the art. FIG. 13 illustrates an example of logic mechanization using conventional symbols for diodes, resistors, and voltage supplies. The example relates to recirculating the B register shown in FIG. 12. The B41 flip flop (which may be constructed as set forth in FIG. 14) is gated by a clock 80. The other flip flops shown are also gated by clock 80. Flip flops 13a, D2, B1 act to set flip flop B41 to its one state. The same flip flops with B1 set to its zero state (Bl) act to set flip flop B41 to its zero state.

Flip flop B40 is similarly set by flip flops D5, D4, and B41.

A discussion of logic gates may be found in Digital Computer Components and Circuits :by R. K. Richards, 1959. FIG. 14 illustrates an example represented by the box symbols in other figures. The flip flop B41 illustrated in FIG. 14 shows two transistors 83 and 84, one of which conducts when in input is received at the 1 input terminal. The other conducts when an input is received at the 0 input terminal provided a clock pulse from clock 80 is also received. If one transistor conducts, the other is shut off. .Therefore, a '-l2 v. output is provided at terminal 82 or 81 depending on whether the flip flop is in its one state or zero state respectively. Flip flop circuits are discussed in Transistor Circuit Engineering by R. F. Shea.

Although only certain selected portions of the logic is mechanized, the remaining logic is mechanized in the same manner as is well known to those skilled in the art.

FLOATING DIVI'DE The following description concerns the floating divide operation. Octal 26 designates floating divide operations. FIGS. 1 through 12 are referred to in connection with this operation.

InDo phase The dividend is assumed to be in the A register originally and the divisor is copied into the B register during this phase. A count of 32 is set up in the G register. During U1 phase one possibility that may occur is overflow which may result from division if the divisor is smaller than or equal to the dividend (B less than or equal to A). Assuming that both numbers are in the normalized forrn' initially, then a one bit de-normalization of the dividend during the U1 phase insures that no division overflow occurs.

It is necessary during the InDo phase, to compare the numbers in the A and B registers to determine which is larger or smaller. If the contents of B are greater than the contents of A then flip flop E0 is one set. However, if A is greater than or equal to B, flip flop E0 is zero set and a one bit de-normalization of the dividend will be' necessary during the U1 phase. The R42 flip flop is one set at T33 time to exclude the exponent from the number comparison. At the end of the InDo phase, flip flop Fm is one set and flip flops R42 and R43 are zero set to prepare for the divide operation that begins in the U1 phase. If B was determined to be greater than A then flip flop D6 is one set to force the operation code to fixed point divide. Cascaded and gates 3gp and M2 are also true for division.

I U] phase The exponent bias is inverted here by inverting bit A40 at T1 time. The inverted .bit is copied directly into A30 at T1 time. During the first word time of this phase the contents of the B register are subtracted from the contents of the A register using standard fixed point subtract logic. After subtracting the fraction parts the difierences are writ-ten back into the A register and precessed one bit left. The exponent difference is written back into the B register. Flip flop R1 is set for gating the B register into the subtractor. The contents of the A register are always shifting into the subtractor. The. contents of the B register recirculate during this operation. The sign of the quotient is determined and stored.

overborrow (A greater than or equal to B) Since Ec flip flop is false for this condition, an one bit de-normalization is necessary to utilize fixed point divide logic and to prevent an overflow. Flip flop D6 is not turned on and therefore the computer is still in operation code 26 (floating divide). The A2 flip flop is'not used as part of the A register in order to right shift by one. The one bit right shift converts from a condition of B less than or equal to A to B greater than A (assuming that the numbers were de-normalized originally) so that an overborrow results from the subtraction of fractional parts or mantissas.

It is necessary to correct for the overborrow condition once again but to do so requires adding two back to the exponent because an extra subtraction of one has occurred. If B had been greater than A, then the carry flip flop would have been on at the end of the first subtraction. Since the subtraction is followed by subtraction of exponents, the one set carry flip flop would cause an extra subtraction in the exponents unless one was added back to cancel out the one set carry flip flop;

Where B is less than or equal to A, however, the fraction must be right shifted by one in order to make B greater than A. The carry flip flop will be one set at the end of the first subtraction of fractions but also since the fraction portion was made smaller by the right shifting (one bit), the exponent must be incremented by one. Hence, for the case B less than or equal to A, two must be added to the exponent. The addition occurs before subtraction using a one-input adder. D6 is used as a carry flip flop and D6 set false means that the carry is on. If the carry is true, A2 will be inverted and read into A1. However, if the number 2 must be added, as indicated above, then instead of reversing A2 into Al, the inversion is delayed by one bit so that in effect two is added to the exponent portion of the A register instead of one.

Overborrow (B greater than A) Since B is greater than A, B flip flop has been set true and no de-normalization of A is required. Flip flop K0: is true at T33 time indicating an overborrow in the case where B is greater than A after subtraction of the mantissas or fractions. This condition must be corrected as it would cause an extra subtraction thereby affecting the exponent. Flip flop Ka is then left on since it cannot be prevented from coming on and the condition is compensated by adding a one in the transfer from A2 to A1. The carry flip =flop for adding in the extra one is D6 so it must be zero set at T31 time. Turning off D6 sets the carry for the one-input addition. The overborrow is corrected by inverting A2 into A1.

Exponent overflow and underflow In dividing a number having a very large exponent in the A register by a number having a very small exponent in the B register, an exponent overflow may occur. If the reverse is true an exponent underflow condition may occur. Flip flop I0 is utilized to detect these conditions. Termination does not occur however for either of these. conditions.

Zero divisor If dividing by zero, an overflow will result and it is necessary to terminate immediately. The overflow flip flop J0 is turned on and also Kc is turned on which terminates the operation.

Zero dividend If the dividend is zero, it is also necessary to terminate immediately. Flip flop D3 is turned off to force operation code 22 in the computer. Operation code 22 is then converted into operation code 6 2 by turning D6 on. Flip flop Kc is turned on to terminate the operation and the entire quotient is forced to zero including the exponent.

Assuming however that the special cases have been dispensed with, or have never occurred, operation code 66 for fixed point divide is then changed to operation code 72 (subtraction) by one setting the D4 flip flop. The exponent difference cannot be copied into the A register so it is copied into the B register into bit position B40. At the end of the U1 phase the operation code 72 is conveted back to code 66 by zero setting D4 at T41 time. Code 66 is then converted into code 67 by one setting D1 to force addition during the second word time because of the overborrow that occurs during the first word time of division.

Ui phase The phase is the same as the fixed point divide operation. It is the same every word time and it continues for 31 word times. R1 is turned on from T1 through T32 times so that the contents of the B register are gated into the subtractor or adder during this period.

The quotient bits end up in the R register in the R32 through R2 bit positions at the end of the Ui phase. After 32 word times, D0 must be set to enter phase Ui-Do which is the last word time of the divide operation. Flip flop C1 senses the last word count and one sets D0 to enter UiDo phase.

UiDo phase The quotient bits are copied into the A register during this phase by copying the R42 flip flop into A41 and shifting right. At T32 time the flip flop D4 is turned on to convert to operation code 77 which is clear and add. Gate M is true by one setting the D4 flip flop. Since this is true, the exponent of the quotient is copied from the B register into the A register into bit positions A41 and shifted right. The sign insertion takes place by copying C2 into A41 at T41 time. Final termination is initiated by turning on Kc flip flop.

SUMMARY The floating point divide operation uses 34 word times. Initially the A register contains the dividend operand and during the first word time the divisor operand is copied into the B register. A count of 32 is set up in the G register. The divisor and dividend operands, comprised of an exponent portion and a fraction portion, are compared and flip flop EC is appropriately set. If the fraction portion of B is greater than A then fixed point divide mode is set. If the fraction portion of B is less than or equal to A, however, the computer remains in the floating point divide mode. In the second Word time the dividend is de-normalized to make the fraction portion of B greater than the fraction portion of A, fixed point divide is then entered. The fraction portion (mantissa) in B is subtracted from the fraction portion (mantissa) in A and copied back into A and precessed left one bit. Also during this word time the exponent bias is inverted. The exponent in B is subtracted from th exponent in A and the result is copied into B. Whatever corrections are necessary are performed. The B register is recirculated so that the divisor is unchanged. The sign of the quotient is determined and stored. The J0 flip flop is set for exponent overflow or underflow or for zero divisor. If there is a zero divisor or dividend then the operation is terminated at the end of this word time. During the third phase, which utilizes 31 word times of the floating divide operation, the numbers are divided using fixed point divide logic and the quotient bits are copied into the R register. The floating divide logic is mechanized to use the Von Newman process of division, for example:

The fractional part of the dividend is in the A register and the fractional part of the divisor is in the B register.

(A register) dividend (B register) divisor Subtraction is performed to determine if an overborrow occurs, it overborrow occures a quotient bit of zero (qi=0) is indicated and stored in the R register, then the divisor is shifted right 1 bit and added back to the partial remainder resulting from the subtraction. If the subsequent addition yields an overcarry a first partial quotient bit of l (q =1) is indicated and the next step will involve shifting the divisor right and subtracting from the the sum of the previous additions. The partial quotient bit is again stored in the R register. If no overborrow occurs as is illustrated by the results of step 3, then the quotient bit equals 1 (9 :1). The divisor is next shifted right and subtracted from the partial remainder. If an overborrow occurs the quotient bit equals zero (q4=0) and the divisor is shifted right and added back as in step 1. Then if overcarry occurs the quotient bit equals 1 (0 1). The serial combining of all quotient bits, often referred to as the partial quotient, forms the final quotient.

00101100 (Step 3) 00001111 40010110 (Step 4 Over-carry 11111001 +00001011 (Step 5) Final quotient= 1101 (A register) 9 The Do flip flop is turned on the last word time of the floating divide operation, the quotient bits are copied into the A register from R with the exponent bits copied from B into A. The stored sign is copied into the A register and the divide operation is terminated.

Logical equations A computer utilizing the concept of the invention was set forth and described in the patent application previously vreferred to. Such computer is also set forth in the logical equations included below. The computer incorporates 48 flip flops (bistable multivibrators or some other suitable bistable device) whose states are determined in accordance With the logical propositions set forth in the equations. For brevity and clarity, in some instances, symbols are used to indicate the settings of two or more flip flops. Such symbols and their meanings are also set forth. In addition, there are constructed several special gates operated according to the existence of two or more conditions. Various flip flops such as G1, Z1, B1 and A3 do not appear in the logical equations inasmuch asthey are driven directly by the memory read heads or amplifiers. The logical equations are as follows:

LOGICAL EQUATIONS FOR FLIP FLOPS 

16. IN AN ELECTRONIC DIGITAL COMPUTER, MEANS PROVIDING FLOATING POINT DIVISION OF ONE OPERAND BY ANOTHER, SAID DIVISION YIELDING A FINAL QUOTIENT; EACH OF SAID OPERANDS HAVING A SIGN ASSOCIATED WITH SAID OPERAND, AND EXPONENT PORTION BEING COMPRISED OF BITS INDICATING A POWER TO WHICH THE NUMBER 2 IS TAKEN, THE NUMERICAL VALUE INDICATED BY SAID EXPONENT PORTION BEING BIASED SO SAID EXPONENT PORTION IS CAPABLE OF INDICATING EITHER POSITIVE OR NEGATIVE EXPONENTS, AND A FRACTION PORTION ALSO BEING COMPRISED OF BITS; ONE OF SAID OPERANDS BEING A DIVISOR OPERAND AND ONE OF SAID OPERANDS BEING A DIVIDEND OPERAND; FIRST REGISTER MEANS FOR HOLDING SAID DIVIDEND OPERAND; SECOND REGISTER MEANS FOR HOLDING SAID DIVISOR OPERAND, THIRD REGISTER MEANS FOR COUNTING DOWN THE NUMBER OF WORD TIMES REQUIRED TO COMPLETE SAID FLOATING DIVIDE OPERATION; FOURTH REGISTER MEANS. MEANS FOR COMPARING SAID DIVISOR OPERAND WITH SAID DIVIDEND OPERAND TO SEE IF SAID DIVIDEND OPERAND IS GREATER THAN SAID DIVISOR OPERAND, MEANS FOR RIGHT SHIFTING SAID DIVIDEND OPERAND IF SAID DIVIDEND OPERAND IS GREATER THAN THE DIVISOR OPERAND INCLUDING MEANS FOR ADDING ONE TO THE EXPONENT PORTION OF SAID DIVIDEND, INCLUDING MEANS FOR SUBTRACTING SAID FRACTION PORTION OF SAID DIVISOR FROM SAID FRACTION PORTION OF SAID DIVIDEND AND FOR COPYING AND LEFT SHIFTING THE DIFFERENCE INTO SAID FIRST REGISTER; MEANS FOR SUBSTRACTING SAID EXPONENT PORTION OF SAID DIVISOR FROM SAID EXPONENT PORTION OF SAID DIVIDEND AND FOR COPYING THE RESULTS THEREOF INTO SAID SECOND REGISTER, SAID SUBTRACTION OF EXPONENTS YIELDING A DIFFERENCE EXPONENT, SAID DIFFERENCE EXPONENT BEING THE EXPONENT CONTAINED IN SAID FINAL QUOTIENT; MEANS FOR DETERMINING EXPONENT OVERFLOW OR UNDERFLOW, AS THE CASE MAY BE, AND FOR SETTING THE OVERFLOW INDICATOR; MEANS FOR RECIRCULATING SAID SECOND REGISTER FOR PRESERVING SAID DIVISOR OPERAND THEREIN; MEANS FOR DETERMINING AND STORING SAID SIGN OF SAID DIVISION QUOTIENT; MEANS FOR DETERMINING IF EITHER SAID DIVISOR OR DIVIDEND OPERAND IS EQUAL TO ZERO; MEANS FOR TERMINATING SAID FLOATING DIVIDE OPERATION 